1. Field of the Invention
The present invention relates to a memory device. More specifically, the invention relates to a memory device that includes memory cells each employing a memory element for storing and holding information based on its electric resistance state.
2. Description of the Related Art
In information apparatuses such as computers, high-speed and high-density DRAMs (Dynamic Random Access Memories) are widely used as a random access memory.
However, the DRAM is a volatile memory and therefore loses information when power is cut off. Accordingly, the need for nonvolatile memories, which do not involve the information loss, is increasing.
As nonvolatile memories that are considered to be promising in the future, FeRAMs (ferroelectric memories), MRAMs (magnetic memories), phase-change memories, and resistance variable memories such as programmable metallization cells (PMCs) and RRAMs have been proposed.
These memories can hold written information for a long period without supply of power thereto. In addition, these memories need no refresh operation since they are nonvolatile, and therefore would achieve correspondingly reduced power consumption.
The resistance variable nonvolatile memories such as the PMCs and RRAMs employ, as the memory layer for storing and holding information, a material having a characteristic that its resistance value changes in response to application of voltage or current thereto. Furthermore, these memories have a comparatively simple configuration in which a memory layer is sandwiched between two electrodes and voltage or current is applied to these two electrodes. This simple configuration allows the size of memory elements therein to be decreased easily.
The PMC has a structure in which an ionic conductor containing a certain metal is sandwiched between two electrodes, and the metal contained in the ionic conductor is included in either one of the two electrodes. Thus, the electric property, such as the resistance or capacitance, of the ionic conductor changes when voltage is applied between the two electrodes. The PMC utilizes this characteristic.
Specifically, the ionic conductor is composed of a solid solution of a chalcogenide and a metal (e.g., amorphous GeS or amorphous GeSe), and either one of the two electrodes contains Ag, Cu or Zn (refer to e.g. JP-A-2002-536840, which will be referred to as a first patent document).
As one RRAM, a configuration has been introduced in which a polycrystalline PrCaMnO3 thin film is sandwiched between two electrodes, and application of a voltage pulse or current pulse to the two electrodes greatly varies the resistance of the PrCaMnO3 film as the recording film (refer to e.g. W. W. Zhuang et al., Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM), Technical Digest “International Electron Devices Meeting”, 2002, p. 193, which will be referred to as a first non-patent document). In this RRAM, the polarity of the voltage pulse applied for information recording (writing) is opposite to that of the voltage pulse applied for information erasing.
As another RRAM, a configuration has been introduced in which SrZrO3 (monocrystalline or polycrystalline) doped with a trace of Cr is sandwiched between two electrodes, and applying current from these electrodes varies the resistance of the recording film (refer to e.g. A. Beck et al., Reproducible switching effect in thin oxide films for memory applications, Applied Physics Letters, 2000, vol. 77, pp. 139 to 141, which will be referred to as a second non-patent document).
This second non-patent document shows the I-V characteristic of the memory layer, and according to this, the threshold voltages of recording and erasing are ±0.5 V. According to the second non-patent document, this configuration also allows information recording and erasing through application of a voltage pulse, and the requisite pulse voltage and pulse width are ±1.1 V and 2 ms, respectively. In addition, it is reported that recording and erasing at a higher speed is also possible: operation with a voltage pulse width of 100 ns is possible, and in this case, the requisite pulse voltage is ±5 V.
The present problems of the above-described nonvolatile memories are as follows. In the FeRAMs, it is difficult to carry out non-destructive reading, which enforces implementation of destructive reading and thus leads to a slow reading speed. Furthermore, there is a limitation on the number of times of polarity inversion associated with reading and recording, which limits the number of times of rewriting.
The MRAMs need a magnetic field for recording, and the generation of the magnetic field is attributed to current applied to interconnects. Therefore, a large current amount is needed for recording.
The phase-change memories are memories that implement recording in response to application of voltage pulses with the same polarity and different voltage levels. However, switching of the phase-change memories possibly occurs depending on the temperature, and hence the phase-change memories are problematically sensitive to changes of the environmental temperature.
In the PMC described in the first patent document, the crystallization temperature of the amorphous GeS or amorphous GeSe is about 200° C., and the crystallization of the ionic conductor deteriorates the properties. Therefore, the PMC involves a problem of having insufficient ability to endure high temperatures in steps for fabricating an actual memory element, such as forming steps for a CVD insulating film and a protective film.
The materials of the memory layers proposed for the RRAMs in the first and second non-patent documents are both a crystalline material, which involves the following problems: heat treatment at about 600° C. is necessary; it is extremely difficult to fabricate a single crystal of the proposed materials; and use of a polycrystal makes it difficult to reduce the size of the element because of influence of grain boundaries in the polycrystal.
It is proposed in the above-described documents of the RRAMs that information recording and erasing are implemented through application of a pulse voltage. However, in the proposed configurations, the resistance of the memory layer after recording is different depending on the pulse width of the applied pulse voltage. This dependency of the resistance after recoding on the pulse width indirectly indicates that repetition of application of the same pulse also changes the resistance value.
For example, the first non-patent document reports that, in application of a pulse of the same polarity, the resistance value after recording greatly changes depending on the pulse width of the applied pulse. When the pulse width is as small as 50 ns or less, the rate of a resistance change associated with recording is small. When the pulse width is as large as 100 ns or more, the resistance value has a characteristic that the resistance is not saturated at a certain value but approaches the resistance value before the recording as the pulse width becomes larger. The first non-patent document explains the properties of a memory structure in which a memory layer and a MOS transistor for access control are connected in series to each other to construct a cell, and the cells are arranged in an array. In the explanation of the properties, it is reported that when the pulse width is changed in the range from 10 ns to 100 ns, the resistance value of the memory layer after recording varies depending on the pulse width. It is expected from the characteristic of the memory layer that if the pulse width is further increased and surpasses a certain value, the resistance starts to decrease again.
Specifically, in the RRAM, the resistance value after recording depends on the magnitude of the pulse voltage and the pulse width, and therefore the existence of variation in the magnitude of the pulse voltage and the pulse width results in variation in the resistance value after recording.
Accordingly, if the width of the pulse voltage is shorter than about 100 ns, the rate of a resistance change associated with recording is small, which leads to increased susceptibility to influence of variation in the resistance value after recording, and hence results in difficulty in stable recording.
Therefore, when such a short pulse voltage is used for recording, it is necessary to carry out a process of verifying the contents of information after the recording in order to surely implement recording.
For example, before recording, a process of retrieving and verifying the contents of information that have been recorded in the memory elements (the resistance values of the memory layers) is carried out, and then the recording is implemented in accordance with the relationship between the verified contents (resistance values) and the contents (resistance values) to be recorded. Alternatively, after recording, a process of retrieving and verifying the contents of information recorded in the memory elements is carried out. If the verified resistance values are different from desired resistance values, recording is implemented again to correct the resistances to the desired values.
These procedures including a verifying process lead to a long time period for recording, and hence involve difficulty in overwriting of data at a high speed for example.
In order to solve the above-described problems, a memory device having the following configuration has been proposed (refer to e.g. Japanese Patent Application No. 2004-22121, which will be referred to as a second patent document). Specifically, the memory device includes memory cells that each are formed of a resistance variable memory element (hereinafter, referred to simply as a memory element) and a circuit element connected in series to the memory element. The memory element has a characteristic that its resistance value changes in response to application of a voltage equal to or higher than a threshold voltage to the both ends thereof. When the voltage applied between the both ends of the memory element and circuit element is equal to or higher than a certain voltage that is higher than the threshold voltage, the combined resistance of the memory element and circuit element in the memory cell after transition of the memory element from a high resistance state to a low resistance state becomes an almost constant value irrespective of the magnitude of the voltage. This memory device in the second patent document achieves stable recording and shortening of the time period for information recording.
In one kind of a memory array, memory cells each formed of a memory element and a circuit element (e.g. a MOS transistor) are arranged in a matrix, with one end of the memory element being connected to one end of the MOS transistor in each cell. In the memory array, the gates of the MOS transistors are connected to word lines W provided along the row direction, and the other ends of the MOS transistors are connected to bit lines B provided in the column direction. Such a memory array can be roughly categorized into the following two types depending on the configuration of source lines S connected to the other ends of the memory elements: (1) a memory array in which the source lines and bit lines are parallel to each other (hereinafter, referred to as a bit-source-parallel memory array), and (2) a memory array in which the source lines and bit lines are perpendicular to each other (hereinafter, referred to as a bit-source-perpendicular memory array).
The respective memory arrays will be described below.
In the following description, the operation of changing the state of a memory element from a high resistance state to a low resistance state is defined as writing, and vice versa as erasing. Furthermore, writing under the condition that the bit line potential is higher than the source line potential is defined as writing of data 0, while writing under the condition that the bit line potential is lower than the source line potential is defined as writing of data 1.
(1) Bit-Source-Parallel Memory Array (see FIG. 6)
When writing is carried out for, of the memory cells in a bit-source-parallel memory array, the memory cell indicated by symbol a in FIG. 6 (writing-target memory cell), the following operation is implemented. Specifically, when data 0 is written, the word line connected to the writing-target memory cell (selected word line) is turned to the high level (hereinafter, the H level), and a potential VDD is applied to the bit line connected to the writing-target memory cell (selected bit line) while 0 V is applied to the source line connected to the writing-target memory cell (selected source line). In contrast, when data 1 is written, the selected word line is turned to the H level, and the selected bit and source lines are provided with 0 V and VDD, respectively. The word, bit and source lines that are not connected to the writing-target memory cell (non-selected word, bit and source lines) are provided with 0 V.
At the time of the writing to the writing-target memory cell, as for the memory cell indicated by symbol b in FIG. 6, which is on the same row as the writing-target memory cell, the potential difference between the bit and source lines is 0 V, and hence writing thereto is not carried out although it is connected to the selected word line. In addition, writing is not carried out for the memory cell indicated by symbol c in FIG. 6, which is on the same column as the writing-target memory cell, since it is not connected to the selected word line.
The writing operation of the bit-source-parallel memory array is simple as described above. However, the bit-source-parallel memory array involves the need to arrange two vertical lines of the bit and source lines in each unit memory cell, which leads to an increased memory cell area.
(2) Bit-Source-Perpendicular Memory Array (see FIG. 7)
When writing is carried out for memory cells in a bit-source-perpendicular memory array, the following three writing methods are available: (2-1) a source line drive method, (2-2) an intermediate potential settlement method (2-3), and (2-3) a collective erasing method. The respective writing methods will be described below.
(2-1) Source Line Drive Method
When writing is carried out by the source line drive method for, of the memory cells in a bit-source-perpendicular memory array, the writing-target memory cell indicated by symbol a in FIG. 7, the following operation is implemented. Specifically, when data 0 is written, the selected word line is turned to the H level, and VDD and 0 V are applied to the selected bit and source lines, respectively. In contrast, when data 1 is written, the selected word line is turned to the H level, and 0 V and VDD are applied to the selected bit and source lines, respectively. In addition, the non-selected bit lines are provided with VDD. In both of writing of data 0 and 1, the non-selected word and source lines are provided with 0 V. In writing of data 0, the non-selected bit lines are provided with 0 V.
At the time of the writing to the writing-target memory cell, as for the memory cell indicated by symbol b in FIG. 7, which is on the same row as the writing-target memory cell, the potential difference between the bit and source lines is 0 V, and hence writing thereto is not carried out although it is connected to the selected word line. In addition, writing is not carried out for the memory cell indicated by symbol c in FIG. 7, which is on the same column as the writing-target memory cell, since it is not connected to the selected word line.
The bit-source-perpendicular memory array includes the bit and source lines perpendicular to each other, and therefore is allowed to have a reduced memory cell area compared with the bit-source-parallel memory array.
However, if the source line drive method is used for the bit-source-perpendicular memory array, in writing of data 1, VDD needs to be applied to the non-selected bit lines in linkage with application of VDD to the selected source line, which results in increased power consumption. In addition, when writing of both data 0 and data 1 is carried out for the memory cells on the same row, both 0 V and VDD need to be applied to the selected source line, i.e., the source line potential needs to be set twice: to 0 V and VDD, which needs two cycles.
(2-2) Intermediate Potential Settlement Method
When writing is carried out by the intermediate potential settlement method for, of the memory cells in a bit-source-perpendicular memory array, the writing-target memory cell indicated by symbol a in FIG. 7, the following operation is implemented. Specifically, when data 0 is written, the selected word line is turned to the H level, and VDD is applied to the selected bit line while an intermediate potential between 0 V and VDD (e.g., VDD/2) is applied to the selected source line. In contrast, when data 1 is written, the selected word line is turned to the H level, and 0 V is applied to the selected bit line while the intermediate potential between 0 V and VDD (e.g., VDD/2) is applied to the selected source line. The non-selected word lines are provided with 0 V, while the non-selected bit and source lines are provided with the intermediate potential between 0 V and VDD (e.g., VDD/2).
At the time of the writing to the writing-target memory cell, as for the memory cell indicated by symbol b in FIG. 7, which is on the same row as the writing-target memory cell, the potential difference between the bit and source lines is 0 V, and hence writing thereto is not carried out although it is connected to the selected word line. In addition, writing is not carried out for the memory cell indicated by symbol c in FIG. 7, which is on the same column as the writing-target memory cell, since it is not connected to the selected word line.
Also as described above, the bit-source-perpendicular memory array includes the bit and source lines perpendicular to each other, and therefore is allowed to have a reduced memory cell area compared with the bit-source-parallel memory array. Furthermore, employing the intermediate potential settlement method for the bit-source-perpendicular memory array offers simplified writing operation.
However, in this method, the difference of the potentials applied to the selected bit and source lines is VDD/2, which is smaller than that in the above-described source line drive method and the collective erasing method to be described below.
(2-3) Collective Erasing Method
In the collective erasing method, initially first writing is carried out for all memory cells in advance (for example, VDD is applied to all the bit lines collectively or sequentially with all the source lines being provided with 0 V so that data 0 is written to all the memory cells). Subsequently, second writing that is the opposite data writing to the first writing is carried out in accordance with input data (the selected bit lines are set to 0 V in accordance with the input data with the selected source line being provided with VDD so that data 1 is written).
Also as described above, the bit-source-perpendicular memory array includes the bit and source lines perpendicular to each other, and therefore is allowed to have a reduced memory cell area compared with the bit-source-parallel memory array. In addition, when the collective easing method is used for the bit-source-perpendicular memory array, the potential applied to the source lines is not frequently changed unlike the source line drive method, and therefore high-speed operation is allowed with low power consumption. Furthermore, the difference between the potentials applied to the selected bit and source lines is VDD.
However, in the collective erasing method, random access on each memory cell basis may be impossible. Specifically, in the collective erasing method, initially first writing is carried out for all memory cells in advance, followed by second writing. Therefore, the unit of data writing is the entire memory array (the unit of access for data writing is the entire memory array), and hence random access on each memory cell basis may be impossible.
In the bit-source-parallel memory array and bit-source-perpendicular memory array, processing for isolating memory elements on each one-bit cell basis is necessary.
Therefore, in order to ease the strictness of the patterning accuracy in manufacturing of memory elements to thereby improve the manufacturing yield of the memory elements, a technique has been proposed in which the ion feed layer for the memory elements is not patterned into individual layers for each memory cell but is provided in common to all the memory cells (refer to e.g. Japanese Patent Application No. 2004-214603, which will be referred to as a third patent document).